The power consumption of electrical circuitry has emerged as, perhaps, the single largest threat to the continued advancement of semiconductor technology and its ability to craft new markets through the shrinking of transistor device size. Simply put, the smaller a transistor can be made, the more power will be consumed per transistor (owing to the transistor's faster speed and substrate leakage) and the more transistors can be fit onto a single chip of silicon. The combination of more transistors per chip and greater power consumption per transistor has resulted in some of the more advanced semiconductor chips under development exhibiting excessive heat dissipation.
Semiconductor chip designers are therefore focusing very intensely on re-designing legacy circuitry to consume less power than that of its predecessor design(s). One area of concern is the Static Random Access Memory (SRAM). SRAM stores bits of information in “cells” that contain active (i.e., “on”) transistors. By comparison, Dynamic Random Access Memory (DRAM) stores bits of information in cells that contain passive capacitors.
Because active transistors consume more semiconductor surface area, consume more electrical power, but are faster than passive capacitors, SRAM memories have been relegated to applications requiring fast memory speeds at the expense of high surface area and electrical power consumption. With the present focus on reducing power consumption of electronic circuitry in general and with the high inherent power consumption of SRAM as a whole, SRAM designs have been the subject of intensive re-design efforts to reduce its power consumption characteristics.